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16 internal banks
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Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available
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Bi-Directional Differential Data Strobe
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8 bit pre-fetch
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Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
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Supports ECC error correction and detection
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On-Die Termination (ODT)
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Temperature sensor with integrated SPD
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This product is in compliance with the RoHS directive
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Per DRAM Addressability is supported
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Internal Vref DQ level generation is available
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Write CRC is supported at all speed grades
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CA parity (Command/Address Parity) mode is supported